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RTL8103E-GR rtl8103el-gr integrated fast ethernet controller for pci express? applications datasheet (confidential: development partners only) rev. 1.3 08 august 2008 track id: jatr-1076-21 realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express ii track id: jatr-1076-21 rev. 1.3 copyright ?2008 realtek semiconductor corp. all rights reserve d. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. disclaimer realtek provides this document ?as is?, without wa rranty of any kind, neither expressed nor implied, including, but not limited t o, the particular purpose. realtek may make improvements and/or changes in this document or in the product described in this document at any time. this document could include technical inaccuracies or typographical errors. trademarks realtek is a trademark of realtek semiconductor cor poration. other names mentioned in this document are trademarks/registered trademarks of their respective owners. license this product is covered by one or mo re of the following patents:us5,307,459, us5,434,872, us5,732,094, us6,570,884, us 6,115,776, and us6,327,625. using this document this document is intended for the software engin eer?s reference and provides detailed programming information. though every effort has been made to ensure that th is document is current and accurate, more information may have become available subsequent to the producti on of this guide. in that event, please contact your realtek representative for additional information that may help in the development process. revision history revision release date summary 1.0 2008/05/28 first release 1.1 2008/07/08 corrected typing error 1.2 2008/07/29 updated licensing information 1.3 2008/08/08 added deep slumber mode (dsm) power saving to features list on page 2.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express iii track id: jatr-1076-21 rev. 1.3 table of contents 1. general desc ription ............................................................................................................ ..................................1 2. features ....................................................................................................................... ..................................................2 3. system applications............................................................................................................ ...................................2 4. pin assignments ................................................................................................................ .........................................3 4.1. rtl8103e (64-p in ) .............................................................................................................................. ......................3 4.2. p ackage i dentification ............................................................................................................................... ............3 4.3. rtl8103el (48-p in ) .............................................................................................................................. ....................4 4.4. p ackage i dentification ............................................................................................................................... ............4 5. pin descriptions............................................................................................................... ..........................................5 5.1. p ower m anagement /i solation ..............................................................................................................................5 5.2. pci e xpress i nterface ............................................................................................................................... ..............5 5.3. eeprom ......................................................................................................................... ...........................................6 5.4. t ransceiver i nterface ............................................................................................................................... .............6 5.5. c lock ............................................................................................................................... ..........................................6 5.6. r egulator and r eference ............................................................................................................................... .......6 5.7. led s ............................................................................................................................... ............................................7 5.8. p ower and g round ............................................................................................................................... ...................7 5.9. gpio ........................................................................................................................... ................................................7 5.10. nc (n ot c onnected ) p ins and t est p ins ...............................................................................................................8 6. functional description......................................................................................................... ..............................8 6.1. pci e xpress b us i nterface ............................................................................................................................... .......8 6.1.1. pci express transm itter ........................................................................................................ ................................8 6.1.2. pci expres s receiver ........................................................................................................... ..................................8 6.2. led f unctions ............................................................................................................................... ...........................9 6.2.1. link monitor................................................................................................................... ........................................9 6.2.2. rx led ......................................................................................................................... ..........................................9 6.2.3. tx led ......................................................................................................................... ........................................10 6.2.4. tx/rx led ...................................................................................................................... ......................................10 6.2.5. customizable led configuration ................................................................................................. .......................11 6.3. phy t ransceiver ............................................................................................................................... ....................12 6.3.1. phy transmitter................................................................................................................ ...................................12 6.3.2. phy r eceiver ................................................................................................................... ....................................12 6.4. eeprom i nterface ............................................................................................................................... .................13 6.5. p ower m anagement ............................................................................................................................... ................14 6.6. v ital p roduct d ata (vpd).......................................................................................................................... .........16 6.7. r eceive -s ide s caling (rss) .......................................................................................................................... ........16 6.7.1. receive-side scaling (rss) initia lization ...................................................................................... .......................16 6.7.2. rss operation .................................................................................................................. ....................................17 7. characteristics................................................................................................................ ......................................18 7.1. a bsolute m aximum r atings ............................................................................................................................... .18 7.2. r ecommended o perating c onditions .................................................................................................................18 7.3. c rystal r equirements ............................................................................................................................... ...........18 7.4. t ransformer c haracteristics ............................................................................................................................19 7.5. o scillator r equirements ............................................................................................................................... .....19 7.6. t hermal c haracteristics ............................................................................................................................... ......19 7.7. dc c haracteristics ............................................................................................................................... ................20 7.8. ac c haracteristics ............................................................................................................................... ................21
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express iv track id: jatr-1076-21 rev. 1.3 7.8.1. serial eeprom in terface timing ................................................................................................. .......................21 7.9. pci e xpress b us p arameters ............................................................................................................................... .22 7.9.1. differential transm itter para meters ............................................................................................ ........................22 7.9.2. differential recei ver parameters ............................................................................................... ..........................23 7.9.3. refclk para meters.............................................................................................................. ..............................23 7.9.4. auxiliary signal ti ming parameters ............................................................................................. .......................27 8. mechanical dimensions.......................................................................................................... ............................28 8.1. rtl8103e (64-p in qfn)........................................................................................................................... ...............28 8.2. rtl8103el (48-p in lqfp).......................................................................................................................... ............29 8.3. m echanical d imensions n otes (rtl8103el 48-p in ).........................................................................................30 9. ordering information........................................................................................................... .............................31
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express v track id: jatr-1076-21 rev. 1.3 list of tables t able 1. p ower m anagement /i solation ............................................................................................................................... 5 t able 2. pci e xpress i nterface ............................................................................................................................... ...............5 t able 3. eeprom ......................................................................................................................... ............................................6 t able 4. t ransceiver i nterface ............................................................................................................................... .............6 t able 5. c lock ............................................................................................................................... ...........................................6 t able 6. r egulator and r eference ............................................................................................................................... .......6 t able 7. led s ............................................................................................................................... .............................................7 t able 8. p ower and g round ............................................................................................................................... ....................7 t able 9. gpio p ins ............................................................................................................................... .....................................7 t able 10. nc (n ot c onnected ) p ins ............................................................................................................................... .........8 t able 11. led s elect (io r egister o ffset 17 h ~18 h )..........................................................................................................11 t able 12. c ustomized led s ............................................................................................................................... ....................11 t able 13. eeprom i nterface ............................................................................................................................... .................13 t able 14. a bsolute m aximum r atings ............................................................................................................................... .18 t able 15. r ecommended o perating c onditions .................................................................................................................18 t able 16. c rystal r equirements ............................................................................................................................... ...........18 t able 17. t ransformer c haracteristics ............................................................................................................................19 t able 18. o scillator r equirements ............................................................................................................................... .....19 t able 19. t hermal c haracteristics ............................................................................................................................... ......19 t able 20. dc c haracteristics ............................................................................................................................... ................20 t able 21. eeprom a ccess t iming p arameters ..................................................................................................................21 t able 22. d ifferential t ransmitter p arameters ..............................................................................................................22 t able 23. d ifferential r eceiver p arameters .....................................................................................................................23 t able 24. refclk p arameters ............................................................................................................................... ..............23 t able 25. a uxiliary s ignal t iming p arameters .................................................................................................................27 t able 26. o rdering i nformation ............................................................................................................................... ...........31 list of figures f igure 1. p in a ssignments (rtl8103e 64-p in ) ......................................................................................................................3 f igure 2. p in a ssignments (rtl8103el 48-p in )....................................................................................................................4 f igure 3. r x led............................................................................................................................ ...........................................9 f igure 4. t x led............................................................................................................................ .........................................10 f igure 5. t x /r x led............................................................................................................................ ...................................10 f igure 6. s erial eeprom i nterface t iming ......................................................................................................................21 f igure 7. s ingle -e nded m easurement p oints for a bsolute c ross p oint and s wing ..................................................25 f igure 8. s ingle -e nded m easurement p oints for d elta c ross p oint ...........................................................................25 f igure 9. s ingle -e nded m easurement p oints for r ise and f all t ime m atching ........................................................25 f igure 10. d ifferential m easurement p oints for d uty c ycle and p eriod ...................................................................26 f igure 11. d ifferential m easurement p oints for r ise and f all t ime ...........................................................................26 f igure 12. d ifferential m easurement p oints for r ingback ............................................................................................26 f igure 13. r eference c lock s ystem m easurement p oint and l oading .........................................................................27 f igure 14. a uxiliary s ignal t iming ............................................................................................................................... .......27
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 1 track id: jatr-1076-21 rev. 1.3 1. general description the realtek rtl8103e(l)-gr fast ethernet controller combines an ieee 802.3 10/100base-t compliant media access controller (mac), pci express bus controller, and embedded one-time-programmable (otp) memory. with state- of-the-art dsp technology and mixed-mode signal technology, the rtl8103e(l) offers high-speed tran smission over cat 5 utp cable or cat 3 utp (10mbps only) cable. functions such as crossover detection & auto -correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing r ecovery, and error correction are implemented to provide robust transmission and reception capability at high speeds. the device supports the pci express 1.1 bus interface for host communications with power management, and is compliant with the ieee 802.3u specification for 10/100mbps ethernet. it also supports an auxiliary power auto-detect function, and will auto-c onfigure related bits of the pci power management registers in pci configuration space. the rtl8103e(l) features em bedded one-time-programmable (otp) memory to replace the external eeprom (93c46/93c56). advanced configuration power management in terface (acpi)?power mana gement for modern operating systems that are capable of operati ng system-directed power management (ospm)?is supported to achieve the most ef ficient power management possibl e. pci msi (message signaled interrupt) and msi-x are also supported. in addition to the acpi feature, remote wake -up (including amd magi c packet? and microsoft ? wake-up frame) is supported in both acpi and ap m (advanced power management) environments. to support wol from a deep power down state (e.g., d3co ld, i.e., main power is off and only auxiliary exists), the auxiliary power source must be able to provide the needed power for the rtl8103e(l). the rtl8103e(l) is fully compliant with microsoft ? ndis5, ndis6 (ipv4, ipv6, tcp, udp) checksum and segmentation task-offload (large se nd and giant send) featur es, and supports ieee 802 ip layer 2 priority encoding a nd ieee 802.1q virtual bridged local area network (vlan). the above features contribute to lowering cp u utilization, especially benefiting performance when in operation on a network server. the rtl8103e(l) supports receive side scaling (rss) to hash incoming tcp connections and load-balance received data processing across multiple cpus. rss improves the number of transactions per second and number of connections pe r second, for increased network throughput. the device also features inter-connect pci express technology. pci express is a high-bandwidth, low pin count, serial, interconnect tec hnology that offers significant improvements in performance over conventional pci and also maintains software compatib ility with existin g pci infrastructure. the device embeds an adaptive equalizer in the pcie phy for eas e of system integration and excellent link quality. the equalizer enables the length of the pcb traces to reach 20 inches. the rtl8103e(l) is suitable for multiple market segm ents and emerging applications, such as desktop, mobile, workstation, server, communications platforms, and embedded applications. built-in linear regulators provide the rtl8103e(l)?s core power, as well as reducing layout area and external bom costs. the rtl8103e supports the deep slumber mode (dsm) power saving feature. see the separate dsm application no tes for details (the rtl8103el doe s not support the dsm feature). note: rtl8103 model differences are listed in section 9 orderi ng information, page 31.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 2 track id: jatr-1076-21 rev. 1.3 2. features ? integrated 10/100 transceiver ? auto-negotiation with next page capability ? supports pci express? 1.1 ? supports pair swap/polarity/skew correction ? crossover detection & auto-correction ? wake-on-lan and remote wake-up support ? customizable leds ? microsoft ? ndis5, ndis6 checksum offload (ipv4, ipv6, tcp, udp) and segmentation task-o ffload (large send and giant send) support ? supports full duplex flow control (ieee 802.3x) ? fully complies with ieee 802.3, ieee 802.3u ? supports ieee 802.1p layer 2 priority encoding ? supports ieee 802.1q vlan tagging ? serial eeprom ? embedded otp memory can replace the external eeprom ? transmit/receive on-chip buffer support ? supports power down/link down power saving ? built-in regulator ? supports pci msi (message signaled interrupt) and msi-x ? supports receive-side scaling (rss) ? embeds an adaptive equalizer in pci express phy (pcb traces can reach up to 20 inches) ? supports deep slumber mode (dsm) power saving feature (rtl8103e 64-pin qfn only) ? 64-pin qfn (rtl8103e) & 48-pin lqfp (rtl8103el) green package 3. system applications ? pci express? fast ethernet on mother board, notebook, or embedded system
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 3 track id: jatr-1076-21 rev. 1.3 4. pin assignments 4.1. rtl8103e (64-pin) 123456789 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 mdip0 mdin0 mdip1 mdin1 vctrl12a nc nc nc nc isolateb ee s k eedi/aux eedo eecs test0 vdd 33 vdd33 vdd33 vdd33 clkreqb nc dvdd12 dvdd 12 nc dvdd 12 dvdd12 nc nc nc nc nc evdd12 nc avdd33 nc egnd egnd test1 test3 test5 test2 rtl8103 e led 3 led 2 led 1 led 0 ckxtal 2 ckxtal 1 rset vctrl12 d 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 3 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 7 nc hson hsop refclk_m refclk_p hsin hsip perstb lanwakeb 65 gnd ( exposed pad) dvdd12 mapin 0 mapin 1 test4 gpi gpo figure 1. pin assignments (rtl8103e 64-pin) 4.2. package identification green package is indicated by a ?g? in the location marked ?t? in figure 1. the version is shown in the location marked ?v?.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 4 track id: jatr-1076-21 rev. 1.3 4.3. rtl8103el (48-pin) 1 2 3 4 5 6 7 8 9 101112 36 35 34 33 32 31 30 29 28 27 26 avdd33 mdip0 mdip1 nd nc 12 nc lanwa k led1/eesk led3/eedo nc perstb dvdd12 isolateb led0 nc hsip mdin0 mdi n1 nc nc hsin gndtx vctrl12a vctrl12d vddtx dvdd12 eecs vdd33 nc ckxtal1 ckxtal2 gnd rset 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 nc nc hson hsop refclk_m refclk _ p gnd dvdd 12 gnd vdd33 nc 25 clkr e q b nc led2/eedi g d d v d e b /aux figure 2. pin assignments (rtl8103el 48-pin) 4.4. package identification green package is indicated by a ?g? in the location marked ?t? in figure 2. the version is shown in the location marked ?v?.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 5 track id: jatr-1076-21 rev. 1.3 5. pin descriptions the signal type codes below are used in the following tables: i: input s/t/s: sustained tri-state o: output o/d: open drain t/s: tri-state bi-direc tional input/output pin 5.1. power management/isolation table 1. power management/isolation symbol type pin no (64-pin) pin no (48-pin) description lanwakeb o/d 19 26 power management event: open drain, active low. used to reactivate the pci expres s slot?s main power rails and reference clocks. isolateb i 36 28 isolate pin: active low. used to isolate the rtl8103e(l) from the pci express bus. the rtl8103e(l) will not drive its pci express outputs (excluding lanwakeb) and will not sample its pci express input as long as the isolate pin is asserted. 5.2. pci express interface table 2. pci express interface symbol type pin no (64-pin) pin no (48-pin) description refclk_p i 26 17 refclk_m i 27 18 pci express differential reference clock source: 100mhz 300ppm. hsop o 29 20 hson o 30 21 pci express transmit differential pair. hsip i 23 15 hsin i 24 16 pci express receive differential pair. perstb i 20 27 pci express reset signal: active low. when the perstb is asserted at power-on state, the rtl8103e(l) returns to a pre-defined reset state and is ready for initialization and configuration after the de -assertion of the perstb. clkreqb o/d 33 25 reference clock request signal. this signal is used by the rtl8103e(l) to request starting of the pci express reference clock.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 6 track id: jatr-1076-21 rev. 1.3 5.3. eeprom table 3. eeprom symbol type pin no (64-pin) pin no (48-pin) description eesk o 48 35 serial data clock. eedi/aux oi 47 34 eedi: output to serial data input pin of eeprom. aux: input pin to detect if aux. po wer exists or not on initial power-on. this pin should be connected to eeprom. to support wakeup from acpi d3cold or apm power-down, this pin must be pulled high to aux. power via a resistor. if this pin is not pulled high to aux. power, the rtl8103e(l) assumes that no aux. power exists. eedo i 45 33 input from serial data output pin of eeprom. eecs o 44 32 eecs: eeprom chip select. 5.4. transceiver interface table 4. transceiver interface symbol type pin no (64-pin) pin no (48-pin) description mdip0 io 3 2 mdin0 io 4 3 in mdi mode, this pair acts as the bi_da+/- pair, and is the transmit pair in 10base-t and 100base-tx. in mdi crossover mode, this pair act s as the bi_db+/- pair, and is the receive pair in 10base-t and 100base-tx. mdip1 io 6 5 mdin1 io 7 6 in mdi mode, this pair acts as the bi _db+/- pair, and is the receive pair in 10base-t and 100base-tx. in mdi crossover mode, this pair acts as the bi_da+/- pair, and is the transmit pair in 10base-t and 100base-tx. 5.5. clock table 5. clock symbol type pin no (64-pin) pin no (48-pin) description ckxtal1 i 60 41 input of 25mhz clock reference. ckxtal2 o 61 42 output of 25mhz clock reference. 5.6. regulator and reference table 6. regulator and reference symbol type pin no (64-pin) pin no (48-pin) description rset i 64 46 reference. external resistor reference.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 7 track id: jatr-1076-21 rev. 1.3 5.7. leds table 7. leds symbol type pin no (64-pin) pin no (48-pin) description led0 o 57 38 led1 o 56 35 led2 o 55 34 led3 o 54 33 leds1-0 00 01 10 11 led0 tx/rx tx/rx tx tx led1 link100 link link link100 led2 link10 full rx link10 led3 na na na na note 1: during power down mode, the led signals are logic high. note 2: leds1-0?s initial value comes from the 93c46. if there is no 93c46, the default value of the (leds1, leds0)=(0, 0). 5.8. power and ground table 8. power and ground symbol type pin no (64-pin) pin no (48-pin) description vdd33 power 16, 37, 46, 53 29, 37 digital 3.3v power supply. dvdd12 power 15, 21, 43, 49, 58 10, 13, 30, 36 digital 1.2v power supply. evdd12 power 28 - analog 1.2v power supply. avdd33 power 2 1 analog 3.3v power supply. gndtx power - 22 analog ground. egnd power 25, 31 - analog ground. gnd power - 7, 14, 31, 47 ground. gnd power 65 - ground (exposed pad). vddtx o - 19 1.2v output. vctrl12d o 63 45 1.2v output supplies power to dvdd12 power pin. vctrl12a o 1 48 1.2v output. note: refer to the most updated schematic circuit for correct configuration. 5.9. gpio table 9. gpio pins symbol type pin no (64-pin) pin no (48-pin) description gpi i 50 - input gpio pin. gpo o 51 - output gpio pin. this pin reflects the link up or link down state. high: link up. low: link down.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 8 track id: jatr-1076-21 rev. 1.3 5.10. nc (not connected) pins and test pins table 10. nc (not connected) pins symbol type pin no (64-pin) pin no (48-pin) description nc - 5, 8, 9, 10, 11, 12, 13, 14, 22, 32, 38, 52, 59, 62 4, 8, 9, 11, 12, 23, 24, 39, 40, 43, 44 not connected. mapin0 io 17 - realtek internal use only mapin1 io 18 - realtek internal use only test0 - 34 - realtek internal use only test1 - 35 - realtek internal use only test2 - 39 - realtek internal use only test3 - 40 - realtek internal use only test4 - 41 - realtek internal use only test5 - 42 - realtek internal use only 6. functional description 6.1. pci express bus interface the rtl8103e(l) complies with pci express base specification revision 1.1, and runs at a 2.5ghz signaling rate with x1 link width, i.e., one transmit and one receive differential pair. the rtl8103e(l) supports four types of pci express messages: inte rrupt messages, error messages, power management messages, and hot-plug messages. to ease pcb layout c onstraints, pci express la ne polarity reversal and link reversal are also supported. 6.1.1. pci express transmitter the rtl8103e(l)?s pci express block receives digital data from the ethernet interface and performs data scrambling with linear feedback shift regi ster (lfsr) and 8b/10b c oding technology into 10-bit code groups. data scrambling is used to reduce the possibility of el ectrical resonance on the link, and 8b/10b coding technology is used to benefit embedded cloc king, error detection, and dc balance by adding an overhead to the system through the addition of 2 extra bits. the data code groups are passed through its serializer for packet framing. the genera ted 2.5gbps serial data is transmitted onto the pcb trace to its upstream device via a differential driver. 6.1.2. pci express receiver the rtl8103e(l)?s pci express block receives 2.5gbps serial data fr om its upstream device to generate parallel data. the receiver?s pll circuits are re-synchronized to main tain bit and symbol lock. through 8b/10b decoding technology and data de-scrambling, the origin al digital data is re covered and passed to the rtl8103e(l)?s internal ethernet mac to be transmitted onto the ethernet media.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 9 track id: jatr-1076-21 rev. 1.3 6.2. led functions the rtl8103e(l) supports four led signals in four different conf igurable operation modes. the following sections describe the various led actions. 6.2.1. link monitor the link monitor senses link in tegrity, such as link10, link 100, or link10/100. whenever link status is established, the specific link led pin is dr iven low. once a cable is disconnected, the link led pin is driven high, indicating th at no network connection exists. 6.2.2. rx led in 10/100mbps mode, blinking of the rx led i ndicates that receive activity is occurring. figure 3. rx led
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 10 track id: jatr-1076-21 rev. 1.3 6.2.3. tx led in 10/100mbps mode, blinking of the tx led i ndicates that transmit activity is occurring. figure 4. tx led 6.2.4. tx/rx led in 10/100mbps mode, blinking of the tx/rx led indicat es that both transmit and receive activity is occurring. figure 5. tx/rx led
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 11 track id: jatr-1076-21 rev. 1.3 6.2.5. customizable led configuration the rtl8103e(l) supports customizable led operat ion modes via io register offset 17h~18h. table 11 describes the different led actions. table 11. led select (io register offset 17h~18h) bit symbol rw description 15:12 ledsel3 rw led select for pinled3 11:8 ledsel2 rw led select for pinled2 7:4 ledsel1 rw led select for pinled1 3:0 ledsel0 rw led select for pinled0 when implementing customized leds: 1. set io register offset 0x55 bit 6 to 1h to enable the customized led function 2. configure io register offset 17h~ 18h to support your own led signals. fo r example, if the value in the io offset 0x17 is 0x8c51h (1000110010100001b) , the led actions are: ? led 0 is only on in 10m mode, with no blinking of tx/rx ? led 1 is only on and with tx/rx blinking in 100m mode ? led 2 is only on and with tx/rx blinking in 100m full duplex mode ? led 3 is only on in full duplex mode table 12. customized leds link act/full speed link 10m link100m not defined - led 0 bit 0 bit 1 bit 2 bit 3 led 1 bit 4 bit 5 bit 6 bit 7 led 2 bit 8 bit 9 bit 10 bit 11 led 3 bit 12 bit 13 bit 14 bit 15 led pin act=0 act=1 link=0 floating led on when full duplex mode link>0 led on when selected speed is linked led blinking when selected speed tx/rx note1: act means blinking tx and rx. link indicates link 10m and link 100m. note2: there are two special modes: mode a: led off mode ? set all bits to 0. mode b: tx/rx mode ? set led 0=0, and either led 1, led 2, or led 3 >0 led 0 = blinking tx/rx. led 1 = follow customized led rule. led 2 = follow customized led rule. led 3= follow customized led rule.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 12 track id: jatr-1076-21 rev. 1.3 6.3. phy transceiver 6.3.1. phy transmitter based on state-of-the-art dsp technology and mixed-mode signa l processing technology, the rtl8103e(l) operates at 10/100mbps over standard cat.5 utp cable (100mbps), and cat.3 utp cable (10mbps). mii (100mbps) mode the transmitted 4-bit nibbles (txd[3:0]) from the ma c, clocked at 25mhz (txc), are converted into 5b symbol code through 4b/5b coding technology, then through scrambling and serializing, are converted to 125mhz nrz and nrzi signals. after that, the nrzi signals are passed to the mlt3 encoder, then to the d/a converter and transmitted onto the media. mii (10mbps) mode the transmitted 4-bit nibbles (txd[3:0]) from the mac, clocked at 2.5mhz (txc), are serialized into 10mbps serial data. the 10mbps serial data is convert ed into a manchester-encoded data stream and is transmitted onto the media by the d/a converter. 6.3.2. phy receiver mii (100mbps) mode the mlt3 signal is processed with an adc, equalizer, blw (baseline wander) correction, timing recovery, mlt3 and nrzi decoder, descrambler, 4b /5b decoder, and is then presented to the mii interface in 4-bit-wide nibbles at a clock speed of 25mhz. mii (10mbps) mode the received differential signal is converted into a manchester-encoded st ream first. next, the stream is processed with a manchester decoder and is de-seria lized into 4-bit-wide nibbles. the 4-bit nibbles are presented to the mii interface at a clock speed of 2.5mhz.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 13 track id: jatr-1076-21 rev. 1.3 6.4. eeprom interface the rtl8103e(l) can use internal efuse memory or an external eeprom. the 93c46/93c56 is a 1k-bit/2k-bit eeprom. the eeprom in terface permits the rtl8103e(l) to read from, and write data to, an external serial eeprom device. note: the rtl8103el only supports 93c46 eeprom. values in the internal efuse memory or external eeprom allow default fields in pci configuration space and i/o space to be overridden following a power-on or software eeprom auto-load command. the rtl8103e(l) will auto-load values from the efuse or eeprom. if the eeprom is not present and efuse auto-load is bypassed, the rtl8103e(l) initializati on uses default values for the appropriate configuration and operational regi sters. software can read and write to the eeprom using bit-bang accesses via the 9346cr register, or using pci vpd (vital product data ). the interface consists of eesk, eecs, eedo, and eedi. the correct eeprom (i.e., 93c46/93c56) must be us ed in order to ensure proper lan function. table 13. eeprom interface eeprom description eecs 93c46/93c56 chip select. eesk eeprom serial data clock. eedi/aux input data bus/input pin to detect whether aux. power exists on initial power-on. this pin should be connected to eeprom. to support wakeup from acpi d3cold or apm power-down, this pin must be pulled high to aux. power via a resistor. if this pin is not pulled high to aux. power, the rtl8103e(l) as sumes that no aux. power exists. eedo output data bus.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 14 track id: jatr-1076-21 rev. 1.3 6.5. power management the rtl8103e(l) is compliant with acpi (rev 1.0, 1.0b, 2.0), pci power manage ment (rev 1.1), pci express active state power management (aspm) , and network device class power management reference specification (v1.0a), such as to support an operating system-directed power management (ospm) environment. the rtl8103e(l) can monitor the ne twork for a wakeup frame, a magi c packet, and notify the system via a pci express power management event (pme) message, beacon, or lanw akeb pin when such a packet or event occurs. then the system can be re stored to a normal state to process incoming jobs. when the rtl8103e(l) is in power down mode (d1 ~ d3): ? the rx state machine is stopped. the rtl8103e(l) monitors the network for wakeup events such as a magic packet and wakeup frame in order to wake up the system. when in power down mode, the rtl8103e(l) will not reflect the status of any in coming packets in the isr register and will not receive any packets into the rx on-chip buffer. ? the on-chip buffer status and packets that have already been received into the rx on-chip buffer before entering power down mode are held by the rtl8103e(l). ? transmission is stopped. pci express transactio ns are stopped. the tx on-chip buffer is held. ? after being restored to d0 stat e, the rtl8103e(l) transmits data that was not moved into the tx on-chip buffer during power down mode. packets that were not transmitted completely last time are re-transmitted. the d3cold_support_pme bit (bit15, pmc register) a nd the aux_i_b2:0 bits (bit8 :6, pmc register) in pci configuration space depend on the existence of aux power. if aux. pow er is absent, the above 4 bits are all 0 in binary. example: if eeprom d3c_support_pme = 1: ? if aux. power exists, then pmc in pci c onfig space is the same as eeprom pmc (if eeprom pmc = c3 ff, then pci pmc = c3 ff) ? if aux. power is absent, then pmc in pci conf ig space is the same as eeprom pmc except the above 4 bits are all 0?s (if eeprom pmc = c3 ff, then pci pmc = 03 7e) in the above case, if wakeup support is desired when main power is off, it is suggested that the eeprom pmc be set to c3 ff (realtek eeprom default value). if eeprom d3c_support_pme = 0: ? if aux. power exists, then pmc in pci c onfig space is the same as eeprom pmc (if eeprom pmc = c3 7f, then pci pmc = c3 7f) ? if aux. power is absent, then pmc in pci conf ig space is the same as eeprom pmc except the above 4 bits are all 0?s (if eeprom pmc = c3 7f, then pci pmc = 03 7e) in the above case, if wakeup support is not desired wh en main power is off, it is suggested that the eeprom pmc be set to 03 7e.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 15 track id: jatr-1076-21 rev. 1.3 magic packet wakeup occurs only when the following conditions are met: ? the destination address of the received magic packet is accepta ble to the rtl8103e(l), e.g., a broadcast, multicast, or unicast packet a ddressed to the current rtl8103e(l) adapter. ? the received magic packet does not contain a crc error. ? the magic bit (config3#5) is set to 1, the pmen bit (config1#0) is set to 1, and the corresponding wake-up method (message, beacon, or lanwakeb) can be asserted in the current power state. ? the magic packet pattern matches, i.e., 6 * ffh + misc (can be none) + 16 * did (destination id) in any part of a valid ethernet packet. a wakeup frame event occurs only wh en the following conditions are met: ? the destination address of the received wakeup frame is acceptable to the rtl8103e(l), e.g., a broadcast, multicast, or unicast addre ss to the current rtl8103e(l) adapter. ? the received wakeup frame does not contain a crc error. ? the pmen bit (config1#0) is set to 1. ? the 16-bit crc* of the received wakeup frame matches the 16-bit crc of the sample wakeup frame pattern given by the local machine?s os. or, the rtl8103e(l) is configured to allow direct packet wakeup, e.g., a broadcast, multic ast, or unicast network packet. note: 16-bit crc: the rtl8103e(l) supports eight l ong wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). the corresponding wake-up method (message, beacon, or lanwakeb) is asserted only when the following conditions are met: ? the pmen bit (bit0, config1) is set to 1. ? the pme_en bit (bit8, pmcsr) in pc i configuration space is set to 1. ? the rtl8103e(l) may assert the corresponding wake-up method (message, beacon, or lanwakeb) in the current power state or in isolation stat e, depending on the pme_support (bit15-11) setting of the pmc register in pci configuration space. ? a magic packet, linkup, or wakeup frame has been received. ? writing a 1 to the pme_status (bit15) of the pmcsr register in the pci configuration space clears this bit and causes the rtl8103e (l) to stop asserting the corr esponding wake-up method (message, beacon, or lanwakeb) (if enabled). when the rtl8103e(l) is in power down mode, e.g., d1-d3, the io and mem accesses to the rtl8103e(l) are disabled. after a pe rstb assertion, the device?s pow er state is restored to d0 automatically if the original power state was d3 cold . there is almost no hardware delay at the device?s power state transition. when in acpi mode, the device does not support pme (power management enable) from d0 (this is the realtek default setti ng of the pmc register auto -loaded from eeprom). the setting may be changed from the eeprom, if required.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 16 track id: jatr-1076-21 rev. 1.3 6.6. vital product data (vpd) bit 31 of the vital product data (vpd) capability structure in th e rtl8103e(l)?s pci configuration space is used to issue vpd read/write commands and is also a flag used to in dicate whether the transfer of data between the vpd data register a nd the 93c46/93c56/93c66 has completed or not. note: the rtl8103el only supports 93c46 eeprom. write vpd register: (write data to the 93c46/93c56/93c66) set the flag bit to 1 at the same time the vpd addr ess is written to write vpd data to eeprom. when the flag bit is reset to 0 by the rtl8103e(l), the vp d data (4 bytes per vpd acc ess) has been transferred from the vpd data register to eeprom. read vpd register: (read da ta from the 93c46/93c56/93c66) reset the flag bit to 0 at the same time the vpd addr ess is written to retrieve vpd data from eeprom. when the flag bit is set to 1 by the rtl8103e(l), the vpd data (4 bytes per vpd access) has been transferred from eeprom to the vpd data register. note1: refer to the pci 2.3 specifi cations for further information. note2: the vpd address must be a dword-aligned address as defined in the pci 2.3 specifications. vpd data is always consecutive 4-byte dat a starting from the vpd address specified. note3: realtek reserves offset 60h to 7fh in eeprom mainly for vpd data to be stored. note4: the vpd function of the r tl8103e is designed to be able to access the full range of the 93c46/93c56/93c66 eeprom, however, the rtl8103el only supports the 93c46 eeprom. 6.7. receive-side scaling (rss) the rtl8103e(l) is compliant with the network dr iver interface specification (ndis) 6.0 receive-side scaling (rss) technology for the microsoft windows family of operating systems. rss allows packet receive-processing from a network adapter to be balanced across th e number of available computer processors, increasing performance on multi-cpu platforms. 6.7.1. receive-side scaling (rss) initialization during rss initialization, the windows operating syst em will inform the r tl8103e(l) to store the following parameters: hash function, hash type, hash bits, indirection table, basecpunumber, and the secret hash key. hash function the default hash function is the toeplitz hash function.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 17 track id: jatr-1076-21 rev. 1.3 hash type the hash types indicate which field of the packet n eeds to be hashed to get the hash result. there are several combinations of these fields, mainl y, tcp/ipv4, ipv4, tcp/ipv6, ipv6, and ipv6 extension headers. ? tcp/ipv4 requires hash calculations over the ipv4 source address, the ipv4 destination address, the source tcp port and the destination tcp port. ? ipv4 requires hash calculations over the ipv4 sour ce address and the ipv4 de stination address. ? tcp/ipv6 requires hash calculations over the ipv6 source address, the ipv6 destination address, the source tcp port and the destination tcp port. ? ipv6 requires hash calculations over the ipv6 s ource address and the ip v6 destination address ( note: the rtl8103e(l) does not support the ip v6 extension header hash type in rss ). hash bits hash bits are used to index the hash result into the indirection table. indirection table the indirection table stores values that are added to the basecpunumber to enable rss interrupts to be restricted from some cpus. the os will update the indirection table to rebalance the load. basecpunumber the lowest number cpu to use for rss. basecpunumber is added to the result of the indirection table lookup. secret hash key the key used in the toeplitz function. for diffe rent hash types, the key size is different. 6.7.2. rss operation after the parameters are set, the rtl8103e(l) will start hash calculation on each incoming packet and forward each packet to its correct qu eue according to the hash result. if the incoming packet is not in the hash type, it will be forwarded to the primary queue. the hash result plus the basecp unumber will be indexed into the indirection table to get the corr ect cpu number. the rtl8103e(l) uses three methods to inform the system of incoming packets: inline interrupt, msi, and msix. periodically the os will update the indirection ta ble to rebalance the load across the cpus.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 18 track id: jatr-1076-21 rev. 1.3 7. characteristics 7.1. absolute maximum ratings warning: absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device reliability will be affected. all voltages are specified reference to gnd unless otherwise specified. table 14. absolute maximum ratings symbol description minimum maximum unit vdd33, avdd33 supply voltage 3.3v -0.3 +0.3 v dvdd12 supply voltage 1.2v -0.12 +0.12 v evdd12 supply voltage 1.2v -0.12 +0.12 v dcinput input voltage -0.3 corresponding supply voltage + 0.5 v dcoutput output voltage -0.3 corresponding supply voltage + 0.5 v n/a storage temperature -55 +125 c note: refer to the most updated schematic circuit for correct configuration. 7.2. recommended operating conditions table 15. recommended operating conditions description pins minimum typical maximum unit vdd33, avdd33 3.0 3.3 3.6 v dvdd12 1.08 1.2 1.32 v supply voltage vdd evdd12 1.08 1.2 1.32 v ambient operating temperature t a - 0 - 70 c maximum junction temperature - - - 125 c note: refer to the most updated schematic circuit for correct configuration. 7.3. crystal requirements table 16. crystal requirements symbol description/condition minimum typical maximum unit f ref parallel resonant crystal reference frequency, fundamental mode, at-cut type. - 25 - mhz f ref stability parallel resonant crystal frequency stability, fundamental mode, at-cut type. t a = 0 c ~ +70 c. -30 - +30 ppm f ref tolerance parallel resonant crystal frequency tolerance, fundamental mode, at-cut type. t a = 25 c. -50 - +50 ppm f ref duty cycle reference clock input duty cycle. 40 - 60 % esr equivalent series resistance. - - 30 ? dl drive level. - - 0.5 mw
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 19 track id: jatr-1076-21 rev. 1.3 7.4. transformer characteristics table 17. transformer characteristics parameter transmit end receive end turn ratio 1:1 ct 1:1 inductance (min.) 350h @ 8ma 350h @ 8ma 7.5. oscillator requirements table 18. oscillator requirements parameter condition minimum typical maximum unit frequency - - 25 - mhz frequency stability t a = 0 c ~ +70 c -30 - +30 ppm frequency tolerance t a = 25 c. -50 - +50 ppm duty cycle - 40 - 60 % jitter - - - 50 ps vp-p - 3.15 3.3 3.45 v rise time - - - 10 ns fall time - - - 10 ns operation temp range - 0 - 70 c 7.6. thermal characteristics table 19. thermal characteristics parameter minimum maximum units storage temperature -55 +125 c ambient operating temperature 0 70 c
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 20 track id: jatr-1076-21 rev. 1.3 7.7. dc characteristics table 20. dc characteristics symbol parameter conditions minimum typical maximum units vdd33, avdd33 3.3v supply voltage - 3.0 3.3 3.6 v evdd12 1.2v supply voltage - 1.08 1.2 1.32 v dvdd12 1.2v supply voltage - 1.08 1.2 1.32 v voh minimum high level output voltage ioh = -4ma 0.9*vdd33 - vdd33 v vo l maximum low level output voltage iol = 4ma 0 - 0.1*vdd33 v vih minimum high level input voltage - 1.8 - - v vil maximum low level input voltage - - - 0.8 v iin input current vin=vdd33 or gnd 0 - 0.5 a icc33 maximum operating supply current from 3.3v - - - 201 ma icc12 maximum operating supply current from 1.2v - - - 127 ma note: refer to the most updated schematic circuit for correct configuration.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 21 track id: jatr-1076-21 rev. 1.3 7.8. ac characteristics 7.8.1. serial eeprom interface timing 93c46(64*16)/93c56(128*16) eesk eecs eedi eedo 11 0 an a2 a0 a1 dn d1 d0 eesk (read) (write) (read) (write) 0 tcs eesk eecs eedi eedo 11 0 an a0 ... dn tcs ... busy ready high impedance high impedance twp eecs eedi eedo eedo (read) (program) status valid tsk tskh tskl tcss tdis tdih tdos tdoh tcsh tsv d0 figure 6. serial eeprom interface timing table 21. eeprom access timing parameters symbol parameter eeprom type min. max. unit tcs minimum cs low time 9346 1000 - ns twp write cycle time 9346 - 10 ms tsk sk clock cycle time 9346 4 - s tskh sk high time 9346 1000 - ns tskl sk low time 9346 1000 - ns tcss cs setup time 9346 200 - ns tcsh cs hold time 9346 0 - ns tdis di setup time 9346 400 - ns tdih di hold time 9346 400 - ns tdos do setup time 9346 2000 - ns tdoh do hold time 9346 - 2000 ns tsv cs to status valid 9346 - 1000 ns
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 22 track id: jatr-1076-21 rev. 1.3 7.9. pci express bus parameters 7.9.1. differential transmitter parameters table 22. differential transmitter parameters symbol parameter min typical max units ui unit interval 399.88 400 400.12 ps v tx-diffp-p differential peak to peak output voltage 0.800 - 1.2 v v tx-de-ratio de-emphasized differential output vo ltage (ratio) -3.0 -3.5 -4.0 db t tx-eye minimum tx eye width 0.75 - - ui t tx-eye-median- to-max-jitter maximum time between the jitter median and maximum deviation from the median - - 0.125 ui t tx-rise , t tx-fall d+/d- tx output rise/fall time 0.125 - - ui v tx-cm-acp rms ac peak common mode output voltage - - 20 mv v tx-cm-dcactive- idledelta absolute delta of dc common mode voltage during l0 and electrical idle 0 - 100 mv v tx-cm-dcline- delta absolute delta of dc common mode voltage between d+ and d- 0 - 25 mv v tx-idle-diffp electrical idle differential peak output voltage 0 - 20 mv v tx-rcv-detect the amount of voltage change allowed during receiver detection - - 600 mv v tx-dc-cm the tx dc common mode voltage 0 - 3.6 v i tx-short tx short circuit current limit - - 90 ma t tx-idle-min minimum time spent in electrical idle 50 - - ui t tx-idle- setto-idle maximum time to transition to a valid electrical idle after sending an electri cal idle ordered set - - 20 ui t tx-idle-toto- diff-data maximum time to transition to valid tx specifications after leaving an electrical idle condition - - 20 ui rl tx-diff differential return loss 10 - - db rl tx-cm common mode return loss 6 - - db z tx-diff-dc dc differential tx impedance 80 100 120 ? l tx-skew lane-to-lane output skew - - 500+2*ui ps c tx ac coupling capacitor 75 - 200 nf t crosslink crosslink random timeout 0 - 1 ms note1: refer to pci express base specification, rev.1.1, fo r correct measurement environment setting of each parameter. note2: the data rate can be modulated with an ssc (spread spectrum clock) from +0 to -0.5% of the nominal data rate frequency, at a modulation rate in th e range not exceeding 30khz ? 33khz. the +/-300ppm requiremen t still holds, which requires the two communicating ports be modulated such that they never exceed a to tal of 600ppm difference.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 23 track id: jatr-1076-21 rev. 1.3 7.9.2. differential receiver parameters table 23. differential receiver parameters symbol parameter min. typical max. units ui unit interval 399.88 400 400.12 ps v rx-diffp-p differential input peak to peak voltage 0.175 - 1.200 v t rx-eye minimum receiver eye width 0.4 - - ui t rx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median - - 0.3 ui v rx-cm-acp ac peak common mode input voltage - - 150 mv rl rx-diff differential return loss 10 - - db rl rx-cm common mode return loss 6 - - db z rx-diff-dc dc differential input impedance 80 100 120 ? z rx--dc dc input impedance 40 50 60 ? z rx-high-imp-dc powered down dc input impedance 200 k - - ? v rx-idle-det-diffp-p electrical idle detect threshold 65 - 175 mv t rx-idle-det- diffentertime unexpected electrical idle enter detect threshold integration time - - 10 ms l rx-skew total skew - - 20 ns note: refer to pci express base specification, rev.1.1, for correct measurement environment setting of each parameter. 7.9.3. refclk parameters table 24. refclk parameters symbol parameter 100mhz input min max units note rise edge rate rising edge rate 0.6 4.0 v/ns 2, 3 fall edge rate falling edge rate 0.6 4.0 v/ns 2, 3 v ih differential input high voltage +150 - mv 2 v il differential input low voltage - -150 mv 2 v cross absolute crossing point voltage +250 +550 mv 1, 4, 5 v cross delta variation of v cross over all rising clock edges - +140 mv 1, 4, 9 v rb ring-back voltage margin -100 +100 mv 2, 12 t stable time before v rb is allowed 500 - ps 2, 12 t period avg average clock period accuracy -300 +2800 ppm 2, 10, 13 t period abs absolute period (including jitter and spread spectrum) 9.847 10.203 ns 2, 6 t ccjitter cycle to cycle jitter - 150 ps 2 v max absolute max input voltage - +1.15 v 1, 7 v min absolute min input voltage - -0.3 v 1, 8 duty cycle duty cycle 40 60 % 2
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 24 track id: jatr-1076-21 rev. 1.3 symbol parameter 100mhz input min max units note rise-fall matching rising edge rate (refclk+) to falling edge rate (refclk-) matching - 20 % 1, 14 z c-dc clock source dc impedance 40 60 ? 1, 11 note1: measurement taken from single ended waveform. note2: measurement taken from differential waveform. note3: measured from -150mv to + 150mv on the differential waveform (derived from re fclk+ minus refclk-). the signal must be monotonic through the measurement region for rise and fall time. the 300mv measurement window is centered on the differential zero crossing. see figure 10, page 26. note4: measured at crossing point wh ere the instantaneous voltage value of the rising edge of refclk+ equals the falling edge of refclk-. see figure 7, page 25. note5: refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to all crossing points for this measurement. see figure 7, page 25. note6: defines as the absolute minimum or maximum instanta neous period. this includes cycle to cycle jitter, relative ppm tolerance, and spread spectrum modulation. see figure 9, page 25. note7: defined as the maximum instantaneous voltage including overshoot. see figure 7, page 25. note8: defined as the minimum instantaneous voltage including undershoot. see figure 7, page 25. note9: defined as the total variation of all crossing volta ges of rising refclk+ and falling refclk-. this is the maximum allowed variance in vcross for any particular system. see figure 7, page 25. note10: refer to section 4.3.2.1 of the pci express base specification, revision 1.1 for information regarding ppm considerations. note11: system board compliance measurements must use the test load card described in figure 13, page 27. refclk+ and refclk- are to be measured at the load capacitors cl. single ended probes must be used for measurements requiring single ended measurements. either single ended probes with math or differential probe can be used for differential measurements. test load cl=2pf. note12: t stable is the time the differential clock must maintain a minimum 150mv differential voltage after rising/falling edges before it is allowed to droop back into the v rb 100mv differential range. see figure 12, page 26. note13: ppm refers to parts per million and is a dc absol ute period accuracy specification. 1ppm is 1/1,000,000 th of 100.000000mhz exactly or 100hz. for 300ppm then we have an error budget of 100hz/ppm*300ppm=30khz. the period is to be measured with a frequency counter with measurement window set to 100ms or greater. the 300ppm applies to systems that do not employ spread spectrum or that use common clock source. for systems employing spread spectrum there is an additional 2500ppm nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2800ppm note14: matching applies to rising edge rate for refclk+ and falling edge rate for refclk-. it is measured using a 75mv window centered on the median cross point where refclk+ rising meets refclk- falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. the rise edge rate of refclk+ should be compared to the fall edge rate of refclk-, the maximum a llowed difference should not exceed 20% of the slowest edge rate. see figure 8, page 25. note15: refer to pci express card electromechanical specification, rev.1.1, for correct measurement environment setting of each parameter.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 25 track id: jatr-1076-21 rev. 1.3 figure 7. single-ended measurement points for absolute cross point and swing figure 8. single-ended measurement points for delta cross point figure 9. single-ended measurement points for rise and fall time matching
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 26 track id: jatr-1076-21 rev. 1.3 figure 10. differential measurement points for duty cycle and period figure 11. differential measurement points for rise and fall time figure 12. differential measurement points for ringback
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 27 track id: jatr-1076-21 rev. 1.3 figure 13. reference clock system measurement point and loading 7.9.4. auxiliary signal timing parameters table 25. auxiliary signal timing parameters symbol parameter min max units t pvperl power stable to perstb inactive 100 - ms t perst-clk refclk stable before perstb inactive 100 - s t perst perstb active time 100 - s t fail power level invalid to pwrgd inactive - 500 ns t wkrf lanwakeb rise ? fall time - 100 ns figure 14. auxiliary signal timing
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 28 track id: jatr-1076-21 rev. 1.3 8. mechanical dimensions 8.1. rtl8103e (64-pin qfn) note: the rtl8103e exposed pad size is type 3.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 29 track id: jatr-1076-21 rev. 1.3 8.2. rtl8103el (48-pin lqfp)
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 30 track id: jatr-1076-21 rev. 1.3 8.3. mechanical dimensions notes (rtl8103el 48-pin) notes: 1. to be determined at seating plane -c- 2. dimensions d1 and e1 do not include mold protrusion. symbol dimension in inchs dimension in millimeters d1 and e1 are maximum plastic body size dimensions including mold mismatch. min nom max min nom max 3. dimension b does not include dambar protrusion. a - - 0.067 - - 1.70 dambar cannot be located on the lower radius of the foot. a1 0.000 0.004 0.008 0.00 0.1 0.20 4. exact shape of each corner is optional. a2 0.051 0.055 0.059 1.30 1.40 1.50 5. these dimensions apply to the flat section of the lead b 0.006 0.009 0.011 15 0.22 0.29 between 0.10 mm and 0.25 mm from the lead tip. b1 0.006 0.008 0.010 0.15 0.20 0.25 6. a1 is defined as the distance from the seating plane to c1 0.004 - 0.006 0.09 - 0.16 the lowest point of the package body. d 0.354 bsc 9.00 bsc 7. controlling dimension: millimeter. d1 0.276 bsc 7.00 bsc 8. reference document: jedec ms-026, bbc e 0.354 bsc 9.00 bsc title: 48ld lqfp ( 7x7x1.4mm) e1 0.276 bsc 7.00 bsc package outline drawing, footprint 2.0mm e 0.020 bsc 0.50 bsc leadframe material: l 0.016 0.024 0.031 0.40 0.60 0.80 doc. no. l1 0.039 ref 1.00 ref version 1 0 3.5 9 0 3.5 9 approve page of 1 0 - - 0 - - dwg no. ss048 - p1 2 12 typ 12 typ check date 3 12 typ 12 typ realtek semiconductor corp.
rtl8103e & rtl8103el datasheet integrated fast ethernet controller for pci express 31 track id: jatr-1076-21 rev. 1.3 9. ordering information table 26. ordering information part number package status RTL8103E-GR 64-pin qfn ?green? package rtl8103el-gr 48-pin lqfp ?green? package note: see page 3 (rtl8103e) and page 4 (rtl8103el) for package identification information. realtek semiconductor corp. headquarters no. 2, innovation road ii hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com

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